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Altera FPGA

Altera is the leading vendor for FPGA solutions for DSP using their C to H compiler and NIOS II processors. The means by which the Altera FPGAs accomplish this is discussed here.

DSP is all about performance and cost/performance. The two main approaches to implement DSP algorithms are:

  • Dedicated hardware – traditionally very expensive
  • Software based algorithms: implemented on a DSP to reduce costs

The second solution is the one that has traditionally been used to reduce the cost of systems because dedicated hardware has been too expensive. Over the past few years, FPGA solutions using Verilog or VHDL have been used to attack the dedicated hardware and ASIC costs and significant gains in cost/performance have been realized.

Altera's C to H compiler offers a much better alternative to approaches using VHDL and Verilog. Now, software algorithms written in C can be transformed into hardware using this compiler. The user no longer has to waste months implementing VHDL, they simply use C to H and the resulting file programs your Altera FPGA.

The combination of the Altera C to H compiler, NIOS II processor and the DSPnano RTOS with the DSP libraries can now transform DSP systems. Here is how it works:

  1. The C to H compiler is used to implement the DSP libraries which are part of DSPnano RTOS. This approach allows the user to realize complex functions normally implemented in software directly in hardware. Over 650 routines are available for transformation; however, only 16 bit fixed point implementation is supported today.
  2. NIOS II is integrated into the picture with its Eclipse based development platform. It can do overall control, handle user interface functions, diagnostics, and a variety of less demanding signal processing functions.
  3. DSPnano RTOS also uses Eclipse IDE and it integrates seamlessly with NIOS II, allowing debugging of the applications running on the RTOS and providing a complete I/O solution for the application.
  4. Now, tradeoffs between running algorithms in hardware and software can be made, allowing NIOS II to process in software those parts of the application that make sense from an overall flexibility and performance point of view and allowing all demanding frontend signal processing functions to be implemented in hardware.

For signal processing developers this is a huge step forward. Demanding routines are implemented in hardware with the ability to handle multiple complex control events in software. As elements become more deterministic and bigger FPGAs become available, they can be moved into hardware, leaving room for more software features.